Technical Field
This Patent Disclosure relates generally to resistor ladder DACs (digital to analog converters), and more particularly to multi-level, multi-ladder DACs.
Related Art
Multi-level resistor ladder DACs can be used to provide extended voltage. The DAC can be configured with switch-interconnect first and second level resistor ladders, with the second-level ladder used to subdivide the voltage range present across a given resistor in the first-level ladder. For example, one possible configuration for a 12 bit DAC would consist of two ladders, with the first consisting of 64 resistors and the second, 63 resistors with 64 tap points. The resistance of all resistors, in both ladders, is the same. When placed in parallel with a given inner ladder resistor, the parallel resistance of the two ladders is 63/64 the resistance of an inner ladder resistor itself.
FIG. 1 illustrates a multi-ladder DAC 10 with first and second level resistor ladders L1, L2. The second-level ladder has taps L2T (for example, 64) that feed into a high impedance buffer input (not shown). The second-level ladder is switch-interconnected through L2 transistor switches ST, SB, respectively to the top and bottom first-level ladder nodes just above and below a selected first-level ladder resistor L1Rn (through L1 node switches L1Sw), forming an L1/L2 resistor ladder loop 12. The L2 switches SB, ST have resistance (Rdson) value Rsw, so that the voltage at the top tap point L2TT is actually IxRsw lower than the voltage at the tap point node N1 just above the selected first-ladder resistor L1RN. The voltage at the bottom tap point is actually IxRsw higher than the voltage at the tap point node N2 just below the selected first-ladder resistor L1Rn. This ladder switch-interconnect configuration results in an error at the transition between the selected first-ladder resistor L1Rn, and the first-level ladder resistor LRn-1 just above it equal to 2IRsw (i.e., at L1 tap node N1 which is the top L1 tap node for resistor L1Rn, and the bottom L1 tap node for resistor L1Rn-1). If the switch resistance is half of the ladder resistor resistance, the DNL (differential non-linearity) error is 1 LSB.